? semiconductor components industries, llc, 2002 march, 2002 rev. 0 1 publication order number: bsr58lt1/d bsr58lt1 jfet chopper transistor nchannel depletion maximum ratings rating symbol value unit draingate voltage v dg 40 vdc gatesource voltage v gs 35 vdc gate current i g 50 madc total device dissipation @ t a = 25 c derate above 25 c p d 350 2.8 mw mw/ c lead temperature t l 300 c operating and storage junction temperature range t j , t stg 65 to +150 c electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min max unit off characteristics gatesource breakdown voltage (i g = 1.0 m adc) v (br)gss 40 vdc gate reverse current (v gs = 15 vdc) i gss 1.0 nadc gate source cutoff voltage (v ds = 5.0 vdc, i d = 1.0 m adc) v gs(off) 0.8 4.0 vdc draincutoff current (v ds = 5.0 vdc, v gs = 10 vdc) i d(off) 1.0 nadc on characteristics zerogatevoltage drain current (note 1) (v ds = 15 vdc) i dss 8.0 80 madc static drainsource on resistance (v ds = 0.1 vdc) r ds(on) 60 w drain gate and source gate oncapacitance (v ds = v gs = 0, f = 1.0 mhz) c dg(on) + c sg(on) 28 pf drain gate offcapacitance (v gs = 10 vdc, f = 1.0 mhz) c dg(off) 5.0 pf source gate offcapacitance (v gs = 10 vdc, f = 1.0 mhz) c sg(off) 5.0 pf 1. pulse width = 300 m s, duty cycle = 3.0%. device package shipping ordering information bsr58lt1 sot23 sot23 case 318 style 10 3000/tape & reel 3 2 1 m6 = specific device code m 6 = date code marking diagram m6 m http://onsemi.com 1 drain 2 source 3 gate
bsr58lt1 http://onsemi.com 2 t f , fall time (ns) t r , rise time (ns) t d(on) , turn-on delay time (ns) 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 i d , drain current (ma) figure 1. turnon delay time r k = 0 t j = 25 c j111 j112 j113 v gs(off) = 12 v = 7.0 v = 5.0 v r k = r d 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 i d , drain current (ma) figure 2. rise time r k = r d r k = 0 t j = 25 c j111 j112 j113 v gs(off) = 12 v = 7.0 v = 5.0 v 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 i d , drain current (ma) figure 3. turnoff delay time r k = r d r k = 0 t j = 25 c j111 j112 j113 v gs(off) = 12 v = 7.0 v = 5.0 v t d(off) , turn-off delay time (ns) 1000 1.0 2.0 5.0 10 20 50 100 200 500 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 i d , drain current (ma) figure 4. fall time r k = r d r k = 0 t j = 25 c j111 j112 j113 v gs(off) = 12 v = 7.0 v = 5.0 v typical switching characteristics note 1 the switching characteristics shown above were measured using a test cir- cuit similar to figure 5. at the beginning of the switching interval, the gate voltage is at gate supply voltage (v gg ). the drainsource voltage (v ds ) is slightly lower than drain supply voltage (v dd ) due to the voltage divider. thus reverse transfer capacitance (c rss ) or gatedrain capaci- tance (c gd ) is charged to v gg + v ds . during the turnon interval, gatesource capacitance (c gs ) discharges through the series combination of r gen and r k . c gd must discharge to v ds(on) through r g and r k in series with the parallel combination of ef- fective load impedance (r d ) and drainsource resistance (r ds ). during the turnoff, this charge flow is reversed. predicting turnon time is somewhat difficult as the channel resistance r ds is a function of the gatesource voltage. while c gs discharges, v gs ap- proaches zero and r ds decreases. since c gd discharges through r ds , turnon time is nonlinear. during turnoff, the situation is reversed with r ds in- creasing as c gd charges. the above switching curves show two impedance conditions; 1) r k is equal to r d , which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) r k = 0 (low impedance) the driving source imped- ance is that of the generator. r gen 50 w v gen input r k 50 w r gg v gg 50 w output r d +v dd r t set v ds(off) = 10 v input pulse t r t f pulse width duty cycle 0.25 ns 0.5 ns = 2.0 m s 2.0% r gg r k r d r d (r t 50) r d r t 50 figure 5. switching time test circuit
bsr58lt1 http://onsemi.com 3 r ds(on) , drain-source on-state resistance (ohms) note 2 the zerogatevoltage drain current (i dss ), is the principle de- terminant of other j-fet characteristics. figure 10 shows the relationship of gatesource off voltage (v gs(off) and drain source on resistance (r ds(on) ) to i dss . most of the devices will be within 10% of the values shown in figure 10. this data will be useful in predicting the characteristic variations for a given part number. for example: unknown r ds(on) and v gs range for an j112 the electrical characteristics table indicates that an j112 has an i dss range of 25 to 75 ma. figure 10, shows r ds(on) = 52 ohms for i dss = 25 ma and 30 ohms for i dss = 75 ma. the corre- sponding v gs values are 2.2 volts and 4.8 volts. y fs , forward transfer admittance (mmhos) c, capacitance (pf) r ds(on) , drain-source on-state resistance (ohms) r ds(on) , drain-source on-state resistance (normalized) 2.0 3.0 5.0 7.0 10 20 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 i d , drain current (ma) figure 6. typical forward transfer admittance 1.0 1.5 2.0 3.0 5.0 7.0 10 15 0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30 v r , reverse voltage (volts) figure 7. typical capacitance 200 160 120 80 40 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 v gs , gate-source voltage (volts) figure 8. effect of gatesource voltage on drainsource resistance 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 -70 -40 -10 20 50 80 110 140 170 t channel , channel temperature ( c) figure 9. effect of temperature on drainsource onstate resistance j113 j112 j111 t channel = 25 c v ds = 15 v c gs c gd t channel = 25 c (c ds is negligible) i dss = 10 ma 25 ma 50ma 75ma 100ma 125ma t channel = 25 c i d = 1.0 ma v gs = 0 10 i dss , zero-gate-voltage drain current (ma) figure 10. effect of i dss on drainsource resistance and gatesource voltage 20 30 40 50 60 70 80 90 100 110 120 130 140 150 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 100 90 80 70 60 50 40 30 20 10 0 v gs , gate-source voltage (volts) t channel = 25 c r ds(on) @ v gs = 0 v gs(off)
bsr58lt1 http://onsemi.com 4 package dimensions case 31808 issue ah sot23 (to236) d j k l a c b s h g v 3 1 2 dim a min max min max millimeters 0.1102 0.1197 2.80 3.04 inches b 0.0472 0.0551 1.20 1.40 c 0.0350 0.0440 0.89 1.11 d 0.0150 0.0200 0.37 0.50 g 0.0701 0.0807 1.78 2.04 h 0.0005 0.0040 0.013 0.100 j 0.0034 0.0070 0.085 0.177 k 0.0140 0.0285 0.35 0.69 l 0.0350 0.0401 0.89 1.02 s 0.0830 0.1039 2.10 2.64 v 0.0177 0.0236 0.45 0.60 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. 318-03 and -07 obsolete, new standard 318-08. style 10: pin 1. drain 2. source 3. gate on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. bsr58lt1/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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